1. Field of the Invention
The present invention relates generally to data storage and more particularly to utilizing a reference cell to increase a read accuracy of memory cells from Magnetic Random Access Memory (MRAM) units.
2. Description of the Prior Art
A wide range of presently available media for data storage vary in several attributes including access speed, duration of reliable storage, and cost. Static Random Access Memory (SRAM) is the storage medium with the best access speed for the cost in applications such as cache memories. However, SRAM is volatile, meaning that it only maintains storage while power is continuously applied. Accordingly, computer users endure lengthy waits when they power-up their computers while substantial amounts of data are written from non-volatile but slow media, such as magnetic disks, into much faster random access memory (SRAM).
Flash memory has been proposed as an alternative to SRAM. Flash memory is a solid-state storage medium that provides moderate access times and is non-volatile. However, flash memory has the disadvantage that it has a limited lifetime, on the order of one million cycles per cell, after which it is no longer possible to write to a cell. This lifetime is orders of magnitude too short for a random access memory in most modern computing systems.
Another solid-state storage medium is Magnetic Random Access Memory (MRAM), which employs a Magnetic Tunnel Junction (MTJ) formed of layers of magnetic material. FIG. 1 shows a cross-section of a prior art MRAM unit 10 including an MTJ 12 formed of a pinned-layer 14 and a free-layer 16, which are magnetic layers typically formed of ferromagnetic materials, and a thin dielectric layer 18 disposed between layers 14 and 16. Pinned-layer 14 has a magnetic moment orientation 20 that is fixed from rotating, while free-layer 16 has a magnetic moment orientation 22 that is free to rotate in response to external magnetic fields. Methods of pinning a pinned-layer 14 are well known in the art and include the use of an adjacent antiferromagnetic layer (not shown).
In an MRAM unit 10, a bit of data is encoded in the direction of the magnetic moment orientation 22 of the free-layer 16 relative to the magnetic moment orientation 20 of the pinned-layer 14. As is well known in the art, when the two magnetic moment orientations 20, 22 are parallel the resistance measured across the MTJ 12 is relatively low, and when the two magnetic moment orientations 20, 22 are antiparallel the resistance measured across the MTJ 12 is relatively high. Accordingly, the relative state of the magnetic moment orientations 20, 22, either parallel or antiparallel to one another, can be determined by reading the resistance across the MTJ 12 with a read current. Typical read currents are on the order of 1-50 xcexcA.
In an MRAM unit 10, the state of the bit, parallel or antiparallel and representing 0 or 1, for example, is varied by applying a write current IW, typically on the order of 1-25 mA, through two conductors, a bit line 24 and a digit line 26, situated proximate to the MTJ 12. The intensity of the write current applied to the bit line 24 may be different than that applied to the digit line 26. The bit line 24 and the digit line 26 cross one another at right angles above and below the MTJ 12. As is well known in the art, although the pinned-layer 14 is depicted in FIG. 1 as nearer to the bit line 24, an MRAM unit 10 also functions with the pinned-layer 14 nearer to the digit line 26.
As is well known, a magnetic field develops around an electric current in a wire. Accordingly, two magnetic fields arise when write currents IW are simultaneously applied to both the bit line 24 and the digit line 26. The two magnetic fields combine at the free-layer 16 to determine the magnetic moment orientation 22. The magnetic moment orientation 22 of the free-layer 16 is made to alternate between the parallel and antiparallel states by alternating the direction of the write current IW in either the bit line 24 or the digit line 26. Alternating (by a write control circuit, not shown) the direction of the write current IW in one of the lines 24, 26 reverses the direction of the magnetic field around that conductor and thereby reverses the direction of the combined magnetic field at the free-layer 16.
In an MRAM unit 10, the state of the bit is read by passing a read current IR through the MTJ 12. In these designs a transistor 30 is used to allow the read current IR to flow through the MTJ 12 during a read operation while preventing the write current IW from flowing through the MTJ 12 during a write operation.
A control signal is required to determine which direction the reversible write current IW will flow. Another control signal is required to change the state of the transistor 30 for read and write operations.
A voltage signal VS is produced by sending a read current IR through the MTJ 12. For reading an MTJ MRAM cell, the signal VS from MTJ 12 is compared with a signal VREF from a reference cell at a comparator 200 utilizing amplifier 210 as shown in FIG. 2.
A typical memory cell 300 as shown in FIG. 3A includes a current source 310, an MTJ device 320, an output 330 coupled to a bit line, and a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) switching transistor 340. A resistance of the MTJ device 320 can either be set to a logical xe2x80x9c0xe2x80x9d state, resulting in a low resistance setting, R, or set to a logical xe2x80x9c1xe2x80x9d state, resulting in a high resistance setting, R+xcex94R. Consequently, the signal VS for a low resistance state is
VS(0)=VMOS+IRR
whereas the signal VS for a high resistance state is
VS(1)=VMOS+IR(R+xcex94R)
In both equations, VMOS is a voltage drop across a drain and a source of the MOSFET switching transistor 340. It will be understood that the MOSFET switching transistor 340 may also be of another transistor type, such as a JFET (Junction Field Effect Transistor) or bipolar transistor.
FIG. 3B shows a reference cell 350 including a current source 360, an MTJ device 370 having a resistance R2, a reference output 380 coupled to a bit line, and a MOSFET switching transistor 390. To obtain the best reading performance coupled with high reliability and accuracy, an output signal VREF from reference cell 350 should have a median value between VS(1) and VS(0). For VREF to be between VS(1) and VS(2), R2 would need to be between R and R+xcex94R. Ideally, this leads to                               V          REF                =                              V            MOS                    +                                    I              R                        ⁢                          R              2                                                                        V          REF                =                                                            V                s                            ⁡                              (                1                )                                      +                                          V                s                            ⁡                              (                0                )                                              2                                                  V          REF                =                                            V              MOS                        +                                          I                R                            ⁡                              (                                  R                  +                                      Δ                    ⁢                                          xe2x80x83                                        ⁢                    R                                                  )                                      +                          V              MOS                        +                                          I                R                            ⁢              R                                2                                                  V          REF                =                                            2              ⁢                              V                MOS                                      +                          2              ⁢                              I                R                            ⁢              R                        +                                          I                R                            ⁢              Δ              ⁢                              xe2x80x83                            ⁢              R                                2                                                  V          REF                =                              V            MOS                    +                                    I              R                        ⁡                          (                              R                +                                                      Δ                    ⁢                                          xe2x80x83                                        ⁢                    R                                    2                                            )                                          
Therefore, the resistance R2 of reference cell 350 should preferably be   R  +                    Δ        ⁢                  xe2x80x83                ⁢        R            2        .  
Since a memory cell has a resistance of either R or R+xcex94R, one approach to producing a reference cell with a resistance of   R  +            Δ      ⁢              xe2x80x83            ⁢      R        2  
is to fabricate a reference cell as if it were a memory cell with a slightly different size or shape. However, if fabrication process parameters change, the resistance of a reference cell may not change commensurately with the resistance of a memory cell. This change in the reference cell resistance may result in an inaccurate reference signal. Consequently, the possibility of read error increases (e.g., reading a logical xe2x80x9c0xe2x80x9d from a memory cell set to a high state (logical xe2x80x9c1xe2x80x9d), or vice versa) and read sensitivity (the ability to discern an actual logic state) decreases.
Accordingly, what is desired is a reference cell designed and fabricated with the same shape and size as a memory cell but arranged in such a way so as to provide a summed effective resistance of   R  +                    Δ        ⁢                  xe2x80x83                ⁢        R            2        .  
The present invention provides for a reference cell circuit for a magnetic tunnel junction MRAM, comprising a first magnetic tunnel junction device set to a low resistance state and a second magnetic tunnel junction device set to a high resistance state. A reference cell series unit includes the first magnetic tunnel junction device electrically coupled in series with the second magnetic tunnel junction device. The reference cell series unit has a first end and a second end; the first end is electrically coupled to a first current source and the second end is electrically coupled to a current sink and a second current source.
Another embodiment of the present invention provides for a reference cell circuit for a magnetic tunnel junction MRAM comprising a first series electrical circuit and a second series electrical circuit. The first series electrical circuit includes a first magnetic tunnel junction device set to a low resistance state and a second magnetic tunnel junction device set to a high resistance state. The second magnetic tunnel junction device is electrically coupled to the first magnetic tunnel junction device in series. The second series electrical circuit includes a third magnetic tunnel junction device set to a low resistance state and a fourth magnetic tunnel junction device set to a high resistance state. The fourth magnetic tunnel junction device is electrically coupled to the third magnetic tunnel junction device in series. The first and second series electrical circuits are electrically coupled to each other in parallel.
Another embodiment of the present invention provides for a reference cell circuit for a magnetic tunnel junction MRAM comprising a first parallel electrical circuit and a second parallel electrical circuit. The first parallel electrical circuit includes a first magnetic tunnel junction device set to a low resistance state and a second magnetic tunnel junction device set to a low resistance state that is electrically coupled to the first magnetic tunnel junction device in parallel. The second parallel electrical circuit includes a third magnetic tunnel junction device set to a high resistance state and a fourth magnetic tunnel junction device set to a high resistance state that is electrically coupled to the third magnetic tunnel junction device in parallel. The first and second parallel electrical circuits are electrically coupled to each other in series.
Another embodiment of the present invention provides for a method for reading a magnetic tunnel junction MRAM cell comprising obtaining a first signal from a memory cell and obtaining a second signal from a reference cell. The reference cell includes a first magnetic tunnel junction device set to a low resistance state and a second magnetic tunnel junction device set to a high resistance state. A reference cell series unit includes the first magnetic tunnel junction device electrically coupled in series with a second magnetic tunnel junction device. The reference cell series unit has a first end and a second end; the first end is electrically coupled to a first current source, and the second end is electrically coupled to a current sink and a second current source. The first signal from the memory cell is compared with the second signal from the reference cell, and a determination of a logic state of the memory cell is based on the comparison step between the first signal and the second signal.
Another embodiment of the present invention provides for a method for reading a magnetic tunnel junction MRAM cell comprising obtaining a first signal from a memory cell and obtaining a second signal from a reference cell. The reference cell includes a first series electrical circuit and a second series electrical circuit with the first series electrical circuit having a first magnetic tunnel junction device and a second magnetic tunnel junction device electrically coupled in series. The first magnetic tunnel junction device is set to a low resistance state and the second magnetic tunnel junction device is set to a high resistance state. The second series electrical circuit has a third magnetic tunnel junction device and a fourth magnetic tunnel junction device electrically coupled in series. The third magnetic tunnel junction device is set to a low resistance state and the fourth magnetic tunnel junction device is set to a high resistance state. The first and second series electrical circuits are electrically coupled to each other in parallel. The first signal from the memory cell is compared with the second signal from the reference cell and a determination of a logic state of the memory cell is based on the comparison step between the first signal and the second signal.
Another embodiment of the present invention provides for a method for reading a magnetic tunnel junction MRAM cell comprising obtaining a first signal from a memory cell and obtaining a second signal from a reference cell. The reference cell includes a first parallel electrical circuit and a second parallel electrical circuit. The first parallel electrical circuit has a first magnetic tunnel junction device and a second magnetic tunnel junction device electrically coupled to each other in parallel. The first magnetic tunnel junction device and the second magnetic tunnel junction device are each set to a low resistance state. The second parallel electrical circuit has a third magnetic tunnel junction device and a fourth magnetic tunnel junction device electrically coupled to each other in parallel. The third magnetic tunnel junction device set and the fourth magnetic tunnel junction device are each set to a high resistance state. The first and second parallel electrical circuits are electrically coupled to each other in series. The first signal from the memory cell is compared with the second signal from the reference cell and a determination of a logic state of the memory cell is based on the comparison step between the first signal and the second signal.
Another embodiment of the present invention provides for a method for reading a magnetic tunnel junction MRAM cell comprising obtaining a first signal from a memory cell in a first-half of a circuit, obtaining a reference signal from a reference cell in a second-half of a circuit, and comparing the first signal from the memory cell with the reference signal from the reference cell, and determining a logic state of the memory cell based on the comparison step between the first signal and the reference signal.
Another embodiment of the present invention provides for a memory block cell layout comprising an amplifier/comparator, a plurality of memory cells with the memory cells sorted into columns and rows, a plurality of reference cells with the plurality of reference cells occurring in pairs for each row of the memory cells including a left-half reference cell and a right-half reference cell for each row of the memory cells. The plurality of reference cells and the plurality of memory cells are further divided into a plurality of left-half reference cells, a plurality of left-half memory cells, a plurality of right-half reference cells, and a plurality of right-half memory cells. The plurality of left-half reference cells and the plurality of left-half memory cells are electrically coupled to a first input lead of the amplifier/comparator and the plurality of right-half reference cells and the plurality of right-half memory cells are electrically coupled to a second input lead of the amplifier/comparator. The first input lead and the second input lead are always coupled to receive and accept both a memory cell input from the plurality of memory cells located in a first-half of the memory block and a reference cell input from the plurality of reference cells located in a second-half of the memory block.
Another embodiment of the present invention provides for a reference cell circuit for a magnetic tunnel junction MRAM comprising n-strings of magnetic tunnel junction devices with each of the n-strings including a first plurality of an integral number of about   n  2
magnetic tunnel junction devices electrically coupled in series with each other and a second plurality of an integral number of about   n  2
magnetic tunnel junction devices electrically coupled in series with each other and with the first plurality of magnetic tunnel junction devices. The first plurality of magnetic tunnel junction devices is set to a low resistance state and the second plurality of magnetic tunnel junction devices is set to a high resistance state. The n-strings of magnetic tunnel junction devices are coupled in parallel with each other such that a summed resistance across the reference cell circuit is about   R  +                    Δ        ⁢                  xe2x80x83                ⁢        R            2        ⁢          xe2x80x83        ⁢          ohms      .      
Another embodiment of the present invention provides for a reference cell circuit for a magnetic tunnel junction MRAM comprising a first parallel electrical circuit and a second parallel electrical circuit. The first parallel circuit includes n-strings of magnetic tunnel junction devices; each of the n-strings has a first plurality of an integral number of about   n  2
magnetic tunnel junction devices electrically coupled in series with each other. The first plurality of magnetic tunnel junction devices are each set to a low resistance state. The second parallel circuit includes n-strings of magnetic tunnel junction devices; each of the n-strings has a second plurality of an integral number of about   n  2
magnetic tunnel junction devices electrically coupled in series with each other. The second plurality of magnetic tunnel junction devices are each set to a high resistance state. The first and second parallel electrical circuits are electrically coupled in series with each other such that a summed resistance across the reference cell circuit is about   R  +            Δ      ⁢              xe2x80x83            ⁢      R        2  
ohms.
Another embodiment of the present invention provides for a reference cell circuit for a magnetic tunnel junction MRAM comprising a means for electrically coupling a plurality of magnetic tunnel junction devices so as to produce a summed resistance across the electrically coupled plurality of magnetic tunnel junction devices of about   R  +            Δ      ⁢              xe2x80x83            ⁢      R        2  
ohms.
Another embodiment of the present invention provides for a memory device comprising at least one memory cell utilizing a magnetic tunnel junction MRAM and at least one reference cell associated with and electrically coupled to the memory cell. The reference cell has an effective resistance of about   R  +            Δ      ⁢              xe2x80x83            ⁢      R        2  
ohms.